1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a normal operation mode and a self-refresh mode.
2. Description of the Related Art
In order to reduce power consumption of semiconductor integrated circuits and ensure reliability of internal circuits thereof, semiconductor integrated circuits having internal step-down circuits have been put to practical use. As such a semiconductor integrated circuit, for example, a DRAM (Dynamic Random Access Memory) is disclosed which is configured to include an internal step-down circuit generating first and second internal stepped-down voltages different from each other, and an internal element being driven with the higher voltage of the first and second internal stepped-down voltages generated by the internal step-down circuit in a normal operation mode and being driven with the lower voltage of the first and second internal stepped-down voltages generated by the internal step-down circuit in a self-refresh mode.
In the above-mentioned semiconductor integrated circuit, power consumption of the semiconductor integrated circuit in the self-refresh mode is reduced by reducing supply voltage to the internal element in the self-refresh mode as compared with in the normal operation mode.
On the other hand, however, the internal step-down circuit is used in common in the normal operation mode and in the self-refresh mode, so that power loss of the internal step-down circuit in the self-refresh mode is greater than power consumption in the semiconductor integrated circuit, thereby reducing the power conversion efficiency.
Furthermore, the internal step-down circuit is configured to select one of the first and second internal stepped-down voltages and output the selected voltage as internal stepped-down voltage by controlling a switching operation of an MOS transistor included in a first output circuit for outputting the first internal stepped-down voltage and a switching operation of an MOS transistor included in a second output circuit for outputting the second internal stepped-down voltage. Therefore, when the operation mode of the DRAM is switched, voltage variations of the internal stepped-down voltage are caused by switching on/off of the MOS transistors.